Description

Join our team in Austin, TX, as a digital/RTL engineer specializing in design verification. This position requires a strong background in VLSI verification flows and the ability to develop and maintain verification environments. You will be responsible for ensuring the quality and completeness of digital design blocks through thorough verification strategies and collaboration with design teams.

Company Culture and Environment

Our company fosters a collaborative and innovative work environment where engineers are encouraged to share ideas, challenge the status quo, and work closely with cross-functional teams. We prioritize teamwork and effective communication in order to drive successful project outcomes.

Career Growth and Development Opportunities

We are committed to your professional growth, providing opportunities for continuous learning and skill enhancement within the digital/RTL engineering field. You will have the chance to participate in design reviews and engage with senior engineers, allowing for mentorship and career advancement.

Detailed Benefits and Perks

• Competitive salary commensurate with experience
• Health, dental, and vision insurance
• Retirement savings plan with company matching
• Generous vacation and paid time off policy
• On-site amenities that enhance work-life balance

Compensation and Benefits

• Attractive compensation package based on qualifications and experience
• Comprehensive benefits, including health insurance and retirement plans

Why you should apply for this position today

This role offers a unique opportunity to contribute to cutting-edge digital design projects in a vibrant city known for its tech innovation. By joining our team, you will be able to leverage your experience and skills to make a significant impact in the industry.

Skills

• 5+ years of professional experience in digital/RTL engineering
• At least 3 years of experience in design verification
• In-depth knowledge of VLSI verification flows and concepts
• Proven experience with SystemVerilog + UVM or equivalent frameworks (specman/eRM, SystemC)
• Strong debugging skills and familiarity with waveform analysis tools

Responsibilities

• Plan, architect, and execute verification strategies for digital design blocks
• Develop and maintain verification environments using SystemVerilog and UVM
• Define and implement comprehensive coverage metrics
• Debug RTL functionality in collaboration with design and architecture teams
• Perform coverage collection, analysis, and closure
• Participate in design reviews, test plan creation, and sign-off activities

Qualifications

• 5+ years of professional experience in digital/RTL engineering
• At least 3 years of experience in design verification
• Proven experience completing at least one full block or system verification cycle
• Deep understanding of VLSI verification flows and industry-standard tools
• Strong communication skills for documentation and presentations

Education Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field

Education Requirements Credential Category

• Bachelor’s degree required

Experience Requirements

• Minimum of 5 years of experience in digital/RTL engineering
• At least 3 years in design verification

Why work in Austin, TX

Austin is a thriving tech hub with a vibrant culture, offering a perfect blend of career opportunities and a high quality of life. With a robust music scene, diverse culinary options, and plenty of outdoor activities, Austin provides a dynamic environment for both personal and professional growth.