Mountain View, CA

Doing * Develop and test RTL modules on AMD/Xilinx FPGA devices (required) and ASIC targets

Mountain View, CA

Doing * Develop and test RTL modules on AMD/Xilinx FPGA devices (required) and ASIC targets

Menlo Park, CA

skills Knowledge of FPGA Experience in Xilinx FPGA and Vivado design tools Experience in commercial

Palo Alto, CA

and APU partitions) • Work with AMD/Xilinx on Versal platform tools (Vitis, Petalinux

Palo Alto, CA

) for design and simulation.Experience working with FPGAs (Xilinx preferred) and associated tooling.Strong critical

Sunnyvale, CA

Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow + Proven design verification skills

San Jose, CA

apps for bring-up, initialization, platform & power management of AMD-Xilinx SOCs and Boards.Safety & Security: Responsible

Fremont, CA

Frameworks such as GNU Radio, CubicSDR, SDR++ etc. * Xilinx/AMD Zynq and/or UltraScale+ development experience * Xilinx

San Jose, CA

bootSystem Level Integration: Utilize the AMD (Xilinx) Vivado and Vitis ecosystems to integrate custom

San Jose, CA

**Who We Are:** At Avnet, relationships matter. We are a global, FORTUNE ® 500 technology distributor and solutions company that

San Jose, CA

, Intel, Qualcomm, Mediatek, Nvidia, Xilinx…), hardware vendors (Dell, HP, HPE, Lenovo

Sunnyvale, CA

Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow + Proven design verification skills

Milpitas, CA

Development** + Target high-end FPGAs (Xilinx Versal, Intel Agilex); perform synthesis, P&

Cupertino, CA

Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow + Proven design verification skills

Santa Clara, CA

Timing closure, with emphasis on Synopsys Protocompiler and Xilinx Vivado. + Hands-on experience with lab FPGA debug methodologies

Santa Clara, CA

Protocompiler or Siemens VPS and Xilinx Vivado + Exposure to ASIC design and verification

Cupertino, CA

Lattice Radiant, design constraints, familiarity with AMD (Xilinx) and Lattice FPGA technologies + Strong System

Santa Clara, CA

Protocompiler or Synplify Premier and Xilinx Vivado + Exposure to ASIC design and verification