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        <description><![CDATA[Stay updated with the latest job listings from Get.it]]></description>
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            <title><![CDATA[Senior Standard Cell Library Engineer]]></title>
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    <p>Intel</p>
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    <p>one or more of the following tools: Cadence Virtuoso, Synopsys Custom Compiler, Cadence Abstract Generator</p>
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            <pubDate>Tue, 13 Oct 2026 09:17:00 GMT</pubDate>
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            <title><![CDATA[Contract Hardware Engineer Mid- #26-26416]]></title>
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    <p>US Tech Solutions</p>
    <p>San Jose, CA</p>
    <p>). + Experience with synthesis tools (e.g., Synopsys DC/DCG/FC), Verilog/System </p>
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            <title><![CDATA[Sr. Manager, Foundation IP (Standard Cells & Memories),, Annapurna Labs]]></title>
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    <p>architectures using block-level synthesis and place-and-route benchmarks (Synopsys Fusion Compiler, Cadence Innovus) on representative</p>
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            <pubDate>Sat, 24 Oct 2026 01:52:00 GMT</pubDate>
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            <title><![CDATA[CAD Automation and Mixed-Signal Simulation Engineer]]></title>
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    <p>Apple</p>
    <p>Sunnyvale, CA</p>
    <p>Verisium/Indago, SimVision, AMS Designer), Synopsys (VCS, Verdi), or Siemens (Questa, </p>
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            <title><![CDATA[Physical Design Engineer, Reality Labs Silicon]]></title>
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    <p>Meta</p>
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    <p>physical design EDA tools such as Cadence Innovus, Synopsys ICC2, or equivalent 14. Experience with physical </p>
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            <pubDate>Tue, 22 Sep 2026 18:52:00 GMT</pubDate>
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            <title><![CDATA[Senior Systems Prototyping and Emulation Engineer]]></title>
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            <pubDate>Wed, 20 May 2026 10:09:00 GMT</pubDate>
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            <title><![CDATA[Senior CAD Automation and Mixed-Signal Simulation Engineer]]></title>
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            <title><![CDATA[NVIDIA 2027 Internships: Digital Circuit Design]]></title>
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    <p>NVIDIA</p>
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            <title><![CDATA[NVIDIA 2027 Internships: Hardware Physical Design / VLSI]]></title>
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            <title><![CDATA[Senior FPGA Prototyping Platform Engineer]]></title>
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            <title><![CDATA[Senior FPGA Prototyping Engineer - Hardware]]></title>
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            <title><![CDATA[R&D Engineer IC Design 4]]></title>
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            <title><![CDATA[Sr. Physical Design Engineer, Annapurna Labs]]></title>
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    <p>tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification</p>
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            <title><![CDATA[Sr. Physical Design Engineer, Annapurna Labs]]></title>
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