Santa Clara, CA

, Cadence Innovus, Cadence Voltus, Synopsys/Ansys Lumerical, Synopsys/Ansys Speos

Sunnyvale, CA

design environments. Manage EDA tool ecosystems (Synopsys, Cadence, Siemens EDA), FlexLM licensing

San Jose, CA

work * RTL checks for scan-insertion compatibility using Synopsys Spyglass * Scan-Insertion using Tessent

Milpitas, CA

Own block-level schematic design and verification in Cadence or Synopsys tools, driving designs to production silicon Collaborate with layout

Santa Clara, CA

devices, flows, and tools. + Hands-on experience with Synopsys ProtoCompiler or Synplify Premier, Xilinx

Santa Clara, CA

Oriented Programming, EDA Tools (Cadence, Synopsys) + Depending on the internship role, prior experience or knowledge requirements

Santa Clara, CA

Back-End Verification + EDA Vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as:

Santa Clara, CA

Synthesis, P&R and Timing closure, with emphasis on Synopsys Protocompiler and Xilinx Vivado. + Hands

San Jose, CA

work * RTL checks for scan-insertion compatibility using Synopsys Spyglass * Scan-Insertion using Tessent

San Jose, CA

work * RTL checks for scan-insertion compatibility using Synopsys Spyglass * Scan-Insertion using Tessent

San Jose, CA

TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence

San Jose, CA

TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence

Santa Clara, CA

experience with front-end synthesis and compilation EDA tools, including Synopsys Design Compiler, ZeBu Compiler, and Cadence

Santa Clara, CA

Route (PNR) tool experience on Cadence Innovus and/or Synopsys Fusion Compiler * Timing closure (STA) experience

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

San Jose, CA

Verification: Mentor Calibre (DRC/LVS/PEX) or Synopsys IC Validator. Reliability/Sign-off: Experience

San Jose, CA

work + RTL checks for scan-insertion compatibility using Synopsys Spyglass + Scan-Insertion using Tessent