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        <title><![CDATA[Get.it - Latest Job Listings]]></title>
        <description><![CDATA[Stay updated with the latest job listings from Get.it]]></description>
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            <title><![CDATA[Senior Standard Cell Library Engineer]]></title>
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    <p>Intel</p>
    <p>Folsom, CA</p>
    <p>one or more of the following tools: Cadence Virtuoso, Synopsys Custom Compiler, Cadence Abstract Generator</p>
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            <pubDate>Tue, 13 Oct 2026 09:17:00 GMT</pubDate>
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            <title><![CDATA[HBM SIPI, Staff Engineer]]></title>
            <description><![CDATA[
    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>Experience in circuit simulation such as Keysight ADS and Synopsys HSPICE. + Use AI/ML/LLM for productivity</p>
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            <pubDate>Sun, 14 Jun 2026 19:03:00 GMT</pubDate>
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            <title><![CDATA[SoC Static Timing Analysis (STA) Engineer, HBM]]></title>
            <description><![CDATA[
    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>and temperature conditions. + Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets</p>
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            <pubDate>Sun, 04 Oct 2026 06:55:00 GMT</pubDate>
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            <title><![CDATA[Senior Linux Systems Engineer - EDA Infrastructure]]></title>
            <description><![CDATA[
    <p>NVIDIA</p>
    <p>Sacramento, CA</p>
    <p> experience supporting EDA toolchains (e.g., Synopsys, Cadence) and high-performance compute clusters (e.g. exposure</p>
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            <pubDate>Thu, 01 Oct 2026 00:00:00 GMT</pubDate>
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            <title><![CDATA[HBM SoC Physical Design Engineer]]></title>
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    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent</p>
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            <pubDate>Sun, 30 Aug 2026 07:47:00 GMT</pubDate>
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            <title><![CDATA[HBM SoC RTL Design Engineer]]></title>
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    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens. + Programming or scripting experience</p>
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            <pubDate>Sun, 02 Aug 2026 06:00:00 GMT</pubDate>
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            <title><![CDATA[HBM SoC RTL Design Engineer]]></title>
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    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens. + Programming or scripting experience</p>
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            <pubDate>Thu, 24 Sep 2026 14:19:00 GMT</pubDate>
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            <title><![CDATA[Signal Integrity Engineer – DRAM Product Architecture for AI Systems]]></title>
            <description><![CDATA[
    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>experience with simulation tools such as Keysight ADS, Synopsys HSPICE, or similar circuit modeling environments + Demonstrated</p>
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            <pubDate>Sat, 25 Apr 2026 11:47:00 GMT</pubDate>
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            <title><![CDATA[Intern - HBM SoC Physical Design Engineer]]></title>
            <description><![CDATA[
    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent</p>
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            <pubDate>Fri, 18 Sep 2026 11:52:00 GMT</pubDate>
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            <title><![CDATA[SoC Architecture and Design Engineer, Senior Member of Technical Staff (SMTS)]]></title>
            <description><![CDATA[
    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens. + Programming or scripting experience</p>
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            <pubDate>Wed, 03 Jun 2026 11:03:00 GMT</pubDate>
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            <title><![CDATA[HBM SoC Physical Design Engineer]]></title>
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    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent</p>
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            <pubDate>Sun, 25 Oct 2026 19:07:00 GMT</pubDate>
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            <title><![CDATA[Staff SoC DFT Engineer, HBM]]></title>
            <description><![CDATA[
    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>standard electronic design automation (EDA) tools from Siemens, Synopsys, and/or Cadence for DFT and implementation. + Bachelor</p>
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            <pubDate>Sun, 26 Jul 2026 04:15:00 GMT</pubDate>
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            <title><![CDATA[MTS SoC DFT Engineer, HBM]]></title>
            <description><![CDATA[
    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>standard electronic design automation (EDA) tools from Siemens, Synopsys, and/or Cadence for DFT and implementation. + Bachelor</p>
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            <pubDate>Fri, 02 Oct 2026 11:13:00 GMT</pubDate>
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            <title><![CDATA[Principal ASIC Design Engineer]]></title>
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    <p>Micron Technology, Inc.</p>
    <p>Folsom, CA</p>
    <p>definitions. **Synthesis &amp; Timing** + Execute logic synthesis (Synopsys Design Compiler or Cadence Genus) and drive</p>
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            <pubDate>Sun, 27 Sep 2026 14:58:00 GMT</pubDate>
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