<![CDATA[Get.it - Latest Job Listings]]> https://www.get.it/rss RSS for Node Thu, 08 Oct 2026 08:16:21 GMT <![CDATA[PD Engineer, Annapurna Labs]]> Annapurna Labs (U.S.) Inc.

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

]]> https://clk.get.it/t/3W91-tyBDG1BBvUOAN63PrvPUfLN0CfYwqyndCbnQCxehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGzt6RlKYXTHjNAsRnkQ2aWO/ https://clk.get.it/t/3W91-tyBDG1BBvUOAN63PrvPUfLN0CfYwqyndCbnQCxehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGzt6RlKYXTHjNAsRnkQ2aWO/ Tue, 06 Oct 2026 19:08:00 GMT <![CDATA[PD Engineer, Annapurna Labs]]> Annapurna Labs (U.S.) Inc.

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

]]> https://clk.get.it/t/3W91-tyBDW9AA_APBNm5P7zDXPTN0CfYwqyndCbnQStehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGx0ogvms3e5tRzlONRLQjx6/ https://clk.get.it/t/3W91-tyBDW9AA_APBNm5P7zDXPTN0CfYwqyndCbnQStehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGx0ogvms3e5tRzlONRLQjx6/ Tue, 06 Oct 2026 18:08:00 GMT <![CDATA[PD Engineer, Annapurna Labs]]> Annapurna Labs (u.s.) Inc.

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

]]> https://clk.get.it/t/3W91-tyBC2xBBfUFBtuzPb_EUPDN0CfYwqyndCbnQC9ehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGzwzRJ-4pCTXEPdkMIvQ5Va/ https://clk.get.it/t/3W91-tyBC2xBBfUFBtuzPb_EUPDN0CfYwqyndCbnQC9ehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGzwzRJ-4pCTXEPdkMIvQ5Va/ Tue, 06 Oct 2026 04:00:00 GMT <![CDATA[PD Engineer, Annapurna Labs]]> Annapurna Labs (U.S.) Inc.

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

]]> https://clk.get.it/t/3W91_dSACGlGBPsNA9C3Pb3GVvTN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0m9DstrjFPHGL8ZeTjx58-f/ https://clk.get.it/t/3W91_dSACGlGBPsNA9C3Pb3GVvTN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0m9DstrjFPHGL8ZeTjx58-f/ Sun, 20 Sep 2026 04:00:00 GMT <![CDATA[Physical Design Engineer, Reality Labs Silicon]]> Meta

Sunnyvale, CA

physical design EDA tools such as Cadence Innovus, Synopsys ICC2, or equivalent 14. Experience with physical

]]> https://clk.get.it/t/3W91_dSABmhADvcKA9CxOrvEVvvN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0kkp7OwN57q8IF7oSe3SVNf/ https://clk.get.it/t/3W91_dSABmhADvcKA9CxOrvEVvvN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0kkp7OwN57q8IF7oSe3SVNf/ Tue, 22 Sep 2026 18:52:00 GMT <![CDATA[Senior CAD Automation and Mixed-Signal Simulation Engineer]]> Apple

Sunnyvale, CA

Verisium/Indago, SimVision, AMS Designer), Synopsys (VCS, Verdi), or Siemens (Questa,

]]> https://clk.get.it/t/3W91_diND2hCB_cIB9q1Pr3CVvDN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0mpihJYu4_CSJ7Yuj7dWR-r/ https://clk.get.it/t/3W91_diND2hCB_cIB9q1Pr3CVvDN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0mpihJYu4_CSJ7Yuj7dWR-r/ Sat, 29 Aug 2026 00:30:00 GMT <![CDATA[Senior Systems Prototyping and Emulation Engineer]]> NVIDIA

Santa Clara, CA

devices, flows, and tools. + Hands-on experience with Synopsys ProtoCompiler or Synplify Premier, Xilinx

]]> https://clk.get.it/t/3W91_NyHDWpABPUIA9-yP7DGUffN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0lvnJcdk5XHejprXoZ1mzP-/ https://clk.get.it/t/3W91_NyHDWpABPUIA9-yP7DGUffN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0lvnJcdk5XHejprXoZ1mzP-/ Wed, 20 May 2026 10:09:00 GMT <![CDATA[PD Engineer, Annapurna Labs]]> Annapurna Labs (U.S.) Inc.

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

]]> https://clk.get.it/t/3W91_dqDCG9AA_oIBtiyOrDDU_rN0CfYwqyndCbnQyhehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGxWn-g9-cqBOEBlL1y6nRuX/ https://clk.get.it/t/3W91_dqDCG9AA_oIBtiyOrDDU_rN0CfYwqyndCbnQyhehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGxWn-g9-cqBOEBlL1y6nRuX/ Wed, 13 May 2026 04:00:00 GMT <![CDATA[NVIDIA 2027 Internships: Digital Circuit Design]]> NVIDIA

Santa Clara, CA

Oriented Programming, EDA Tools (Cadence, Synopsys) + Depending on the internship role, prior experience or knowledge requirements

]]> https://clk.get.it/t/3W91_d-CCWZFBfcNBd22Pb_FUvDN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0n9ynakz1lRoBkd6O6CFS5h/ https://clk.get.it/t/3W91_d-CCWZFBfcNBd22Pb_FUvDN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0n9ynakz1lRoBkd6O6CFS5h/ Thu, 20 Aug 2026 11:27:00 GMT <![CDATA[NVIDIA 2027 Internships: Hardware Physical Design / VLSI]]> NVIDIA

Santa Clara, CA

Back-End Verification + EDA Vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as:

]]> https://clk.get.it/t/3W91_d-CCWZFBfAIBdizOrjOXPDN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0kpAFEjJsqCTfmpN6AYfXmE/ https://clk.get.it/t/3W91_d-CCWZFBfAIBdizOrjOXPDN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0kpAFEjJsqCTfmpN6AYfXmE/ Thu, 20 Aug 2026 11:27:00 GMT <![CDATA[Senior FPGA Prototyping Platform Engineer]]> NVIDIA

Santa Clara, CA

Synthesis, P&R and Timing closure, with emphasis on Synopsys Protocompiler and Xilinx Vivado. + Hands

]]> https://clk.get.it/t/3W91_N6HCW5NAPYICtG5Pr7HUfHN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0lOpyEjmggS2lmm43A7ox33/ https://clk.get.it/t/3W91_N6HCW5NAPYICtG5Pr7HUfHN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0lOpyEjmggS2lmm43A7ox33/ Wed, 03 Jun 2026 11:20:00 GMT <![CDATA[Design For Test Engineer IV (IC)]]> Arrow Electronics, Inc.

San Jose, CA

work * RTL checks for scan-insertion compatibility using Synopsys Spyglass * Scan-Insertion using Tessent

]]> https://clk.get.it/t/3W91_diCD2dHBPUKBNy5ObjGVvfN0CfYwqyndCbnQyhehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGzsYQIoPDp2NynbBeL_nHC6/ https://clk.get.it/t/3W91_diCD2dHBPUKBNy5ObjGVvfN0CfYwqyndCbnQyhehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGzsYQIoPDp2NynbBeL_nHC6/ Wed, 01 Apr 2026 04:00:00 GMT <![CDATA[Design For Test Engineer III (IC)]]> Arrow Electronics, Inc.

San Jose, CA

work * RTL checks for scan-insertion compatibility using Synopsys Spyglass * Scan-Insertion using Tessent

]]> https://clk.get.it/t/3W91_dWDC29AA_MKBNC1OrnAVvTN0CfYwqyndCbnQyhehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGx9s_T5VQYxjmJvBOcjHOJE/ https://clk.get.it/t/3W91_dWDC29AA_MKBNC1OrnAVvTN0CfYwqyndCbnQyhehX28JKjOhtMYQCZt0T5oxWJyBGoSagGLfF68fe9OPwY2vCAWzYLttKK-IHoG3PCsrIaZ1Rqts_rK_AHsnGx9s_T5VQYxjmJvBOcjHOJE/ Wed, 22 Jul 2026 04:00:00 GMT <![CDATA[Emulation Front-End Infrastructure Engineer]]> NVIDIA

Santa Clara, CA

experience with front-end synthesis and compilation EDA tools, including Synopsys Design Compiler, ZeBu Compiler, and Cadence

]]> https://clk.get.it/t/3W91_d6BD2dNAfMIAt62MLzOUvDN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0nRJxVE8toiB_q8pQLOcWLg/ https://clk.get.it/t/3W91_d6BD2dNAfMIAt62MLzOUvDN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0nRJxVE8toiB_q8pQLOcWLg/ Wed, 12 Aug 2026 11:42:00 GMT <![CDATA[R&D Engineer IC Design 4]]> Broadcom

San Jose, CA

TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence

]]> https://clk.get.it/t/3W91_NqCBmZAAvQEBNm5OrvFXfHN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0lGGrSMQX8imVQz43lvQJKr/ https://clk.get.it/t/3W91_NqCBmZAAvQEBNm5OrvFXfHN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0lGGrSMQX8imVQz43lvQJKr/ Fri, 03 Jul 2026 09:29:00 GMT <![CDATA[R&D Engineer IC Design 4]]> Broadcom

San Jose, CA

TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence

]]> https://clk.get.it/t/3W91_dyCDGtFD_oKBN63Ob_AUvbN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0m1LGRP_zJ0ozh_eiyQOBSm/ https://clk.get.it/t/3W91_dyCDGtFD_oKBN63Ob_AUvbN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0m1LGRP_zJ0ozh_eiyQOBSm/ Thu, 30 Jul 2026 13:17:00 GMT <![CDATA[PD Engineer, Annapurna Labs]]> Amazon

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

]]> https://clk.get.it/t/3W91_NSMCGZBA_YLA9mwMbDEU_rN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0mlf3jiN00Q_LyOB1r0w_ZC/ https://clk.get.it/t/3W91_NSMCGZBA_YLA9mwMbDEU_rN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0mlf3jiN00Q_LyOB1r0w_ZC/ Sat, 18 Jul 2026 10:27:00 GMT <![CDATA[Sr. Physical Design Engineer, Annapurna Labs]]> Amazon

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

]]> https://clk.get.it/t/3W91_dyACmtDB_QKA923O7rOUfDN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0kzjVo3h9KcQ80XkXCly1xx/ https://clk.get.it/t/3W91_dyACmtDB_QKA923O7rOUfDN0CfYwqyndCbvEXRF0ienZKbawtwcXSVr0T9gvGJyamscagKMHEr-Gvgbd0R_9HUMncGl_7LgZzJDyK7l5MODnFnl4eqZu0kzjVo3h9KcQ80XkXCly1xx/ Wed, 29 Jul 2026 07:34:00 GMT