San Jose, CA

inspiring the world to learn, communicate and advance faster than ever. Perform Synopsys HAPs pre-silicon ASIC prototyping flow - expert

Santa Clara, CA

devices, flows, and tools. + Hands-on experience with Synopsys ProtoCompiler or Synplify Premier, Xilinx

Milpitas, CA

Own block-level schematic design and verification in Cadence or Synopsys tools, driving designs to production silicon Collaborate with layout

Santa Clara, CA

Synthesis, P&R and Timing closure, with emphasis on Synopsys Protocompiler or Siemens VPS and Xilinx

San Jose, CA

derates. **Preferred skills:** + Synthesis Tools: Synopsys. DC/DCG/FC + Formal Verification : Synopsys

Santa Clara, CA

Synthesis, P&R and Timing closure, with emphasis on Synopsys Protocompiler or Synplify Premier and

Mountain View, CA

spins. + Lead technical engagement with EDA vendors (Synopsys, Cadence) to evaluate, qualify, and deploy new signoff tool versions

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

Sunnyvale, CA

Experience with single or multi-FPGA platforms (Synopsys HAPS experience). + Experience writing 'make' based build

Sunnyvale, CA

Experience with single or multi-FPGA platforms (Synopsys HAPS experience). + Experience writing 'make' based build

Sunnyvale, CA

Experience with single or multi-FPGA platforms (Synopsys HAPS experience). + Experience writing 'make' based build

Cupertino, CA

tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification

Sunnyvale, CA

tooling. Hands-on experience with Pre-Si tools like Synopsys Primetime Power Analysis and Post-Si

Sunnyvale, CA

Constraint analysis and debug, using industry standard tools such as Synopsys CA (Constraint Analyzer). + Knowledge of

Sunnyvale, CA

Constraint analysis and debug, using industry standard tools such as Synopsys CA (Constraint Analyzer). + Understand

San Jose, CA

integration using Cadence Innovus/Integrity or Synopsys 3DIC compiler is a must. Candidates should have a

San Jose, CA

work + RTL checks for scan-insertion compatibility using Synopsys Spyglass + Scan-Insertion using Tessent

Cupertino, CA

Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable